A number of two wire bi-directional signal transmission systems have been extensively used. One such system is the Integrated Circuit Bus system (I2C Bus system), disclosed in the Philips Data Handbook IC12a, 1989, and “The I2C Bus and how to use it (including specifications)” 1995 Philips Semiconductors.
The I2C Bus system is a serial bus system between individual integrated circuits, or stations, that are interconnected through a bidirectional two wire transmission channel. Of the two wires, one carries a clock signal, and the other the data, with a predetermined communication protocol. Depending on the particular function within the system, an individual station can act as the transmitter, or as a receiver, or both.
The I2C system uses a data wire (SDA) and clock wire (SCL) which are connected to a positive supply (VCC) through pull-up resistors. When the stations are not communicating the clock and data lines are free, and pulled high by these resistors. Each station which can communicate on the bus has an open collector or open drain output which can pull the bus lines to a low voltage level close to the negative supply (VEE). The sequence in which the SCL and SDA lines are pulled low provides the communication information flow between the integrated circuits sharing that bus.
The number of stations allowed, or the distance over which the bus can communicate is determined by the load presented on the bus line by the total capacitance of each line. That is by the total of the capacitance of the bus wiring, the connections, the integrated circuit pins, and the capacitive load presented by each input/output circuit within the integrated circuit. If the bus capacitance is increased then the maximum possible speed of the bus is limited, and the slower rise times on the bus start to cause difficulties.
A number of design suggestions have been made to overcome the problems of expanding and extending the application of the I2C Bus beyond the limit presented by this capacitive load. Many simple circuits have been published seeking to provide this expanded capability. Most of these circuits have problems which may be associated with latching, be only conditionally stable, or present glitches. The usual limitation presented by such circuits is that they are unable to reverse their direction of signal flow when active, generating a glitch that can upset the bus I2C function. For example a circuit will latch if the receiving logic path goes low and transfers this input low to the output. If this low output is detected as being low and transmitted back along the return path, then this low signal returned to the input as a low will hold the input low, even when the original external low drive signal is removed. Thus the bus has ‘latched’ into this low state. To prevent latching, various circuit techniques have been suggested to break that loop, and yet to still fulfil the required function. Oscillation in such a loop becomes another possible problem.
A more subtle problem arises because the I2C Bus protocol has been defined so that two or more ICs are permitted to transmit (that is pull the I2C bus low) at the same time. All ICs connected to the bus monitor the bus line voltage, including the two or more which have started transmitting. As soon as one of those transmitting ICs detects that the bus has remained LOW although that IC is attempting to transmit a HIGH signal, then that IC will immediately cease transmitting. That is it stops transmitting as soon as it detects the LOW being transmitted by another IC while it was attempting to release the bus line to allow a high state. On detecting such a bus contention, it will stop transmitting and wait to retry at a later opportunity when hopefully there will be no contention.
Most of the circuits that have been suggested as providing a suitable buffering action have a problem that arises during this bus contention function. They fail to buffer the signals in a manner that does not generate spurious signals. To demonstrate this, consider when one side of the buffer circuit is held low, and while the input is still held low another integrated circuit connected to the buffer output generates a low signal. When the original input drive is released, the action of the buffer should be to detect the application of the low on the output side, and therefore the input should continue to hold the input bus low as the input drive ceases. However in all of the published circuits there is a delay between the time the active forward path switches off, and the reverse path is activated. This results in the input pin briefly being pulled high, generating a glitch which can be falsely interpreted by the integrated circuits connected on the input side as a signal pulse. Unfortunately many proposed circuits fail this glitch test, and allow the input to go high for the time needed for the buffer circuit to recognise that the direction of the signal path has reversed.
A solution to the problem of providing an effective buffer circuit is described in U.S. Pat. No. 6,014,040, Bi-Directional Signal Transmission System. In this circuit, which has been realised in the integrated circuit OM1896, the loop between the forward and the reverse buffered signal has been broken by adopting two voltage levels depending firstly on whether the bus is being held low below an input threshold Vref by a station on the I2C side of the buffer, that is on the first bidirectional signal path, an input below this reference voltage Vref therefore activates the forward signal path. The second voltage level Vtt is that generated by a low being transmitted by the reverse path in the buffer, this low being generated on the first bidirectional signal path as an output saturation voltage of the buffer. It is a slightly higher voltage than Vref and is still able to be interpreted by ICs (stations) connected on the input side as a bus low signal. It is therefore a low output signal generated by the reverse path on the first bi-directional signal path, and is a voltage level that is not as low as the threshold voltage of the forward path input comparator. In this way a buffer is created which neither latches, nor does it generate a glitch if the signal direction is reversed through the buffer by the inputs on both sides being held low sequentially, with the low signals overlapping in time.
On the buffered output bus side the OM1896 offers a split output and input path so that it can be interfaced to other ICs in which the transmit and receive paths are separated. For example, where it is necessary to provide optical isolation of the bus paths. If this capability is not needed then the bus out and bus receive pins may be wired together to give a single output connection to the buffer. On the side of the bus connected to the first bi-directional signal path and the I2C stations connected to this path, the difference between the input bus threshold used in the comparator sensing the voltage on that path, and the output saturation voltage generated when a low on the second bi-directional signal path is transmitted along the reverse path back to this input, allows the buffer to determine the direction in which the low signal is being transmitted without latching, and thereby avoids generating glitches when the signal path direction is reversed when the side of the buffer being held low is changed from one to the other side.
When the OM1896 was designed, these two voltage levels, that is Vref, and Vtt, were used to differentiate between a bus LOW signal being transmitted in the forward direction, with the input being held below the input threshold Vref, and a LOW signal output voltage in the reverse direction Vtt which is an output saturation voltage derived from the forward voltage across a diode junction. In a silicon bipolar integrated circuit this diode forward voltage drop is typically about 600 millivolts, and also has a negative temperature coefficient of typically two millivolts per degree Celsius. These typical voltages were acceptable for applications in which the majority of the integrated circuits used in the system were operating at 5 volts. Since then, increased integration, and an emphasis on designing for reduced power consumption, the typical power supply voltage of many I2C devices has fallen to as low as 2.5 volts.
It is an object of the present invention to provide a bi-directional signal transmission system that overcomes or at least substantially ameliorates the problems associated with the prior art.
It is a further object of this invention to overcome the limitations inherent in the design of prior art bi-directional transmission systems to better match the characteristics to those of the integrated circuits, or stations, with which such systems are to be used.